Circuit design method, apparatus, and program

ABSTRACT

A circuit design method able to design a processing circuit for processing a finite field with fewer circuit design elements and in a smaller-size than the past comprising obtaining a first primitive root α 1  on the basis of a first polynomial for a first extension from a first finite field to a second finite field, obtaining a second primitive root α 2  on the basis of a second polynomial for a second extension from the second finite field to a third finite field, wherein a coefficient of a 0-th term is defined using the first primitive root α 1  obtained above and the coefficient of the  0 -th term of the first polynomial, defining processing on the third finite field using a base expressed using the second primitive root α 2 , and designing the processing circuit for performing that processing.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a method, apparatus, and program for designing a processing circuit for performing processing on a finite field.

[0003] 2. Description of the Related Art

[0004] For example, in error correction coding and decoding of the Hamming code etc., for example, processing is performed on a finite field.

[0005] Such a finite field is sometimes defined by extension from another finite field.

[0006] For example, where a second finite field is defined by a first extension from a first finite field and a third finite field is defined by a second extension from the second finite field, the processing on the third finite field is defined using the processing on the second finite field.

[0007] Further, the processing on the second finite field is expressed using a base determined on the basis of a primitive root obtained by a first polynomial for the first extension. Further, the processing on the second finite field is expressed using a base determined on the basis of a primitive root obtained by a second polynomial for the second extension.

[0008] In the conventional circuit design method, a coefficient of the 0-th term of the second polynomial is set without regard as to the coefficient of the 0-th term of the first polynomial.

[0009] Summarizing the problem to be solved by the invention, in the conventional circuit design method explained above, the number of circuit design elements of the processing circuit for processing on the third finite field becomes large, so the processing circuit ends up becoming large in scale.

SUMMARY OF THE INVENTION

[0010] An object of the present invention is to provide a circuit design method, apparatus, and program able to design a processing circuit for processing on a finite field with fewer circuit design elements and in a smaller size than the past and such a processing circuit.

[0011] To attain the above object, according to a first aspect of the present invention, there is provided a circuit design method executed by a computer for designing a processing circuit for processing on a finite field comprising a first step of obtaining a first primitive root a on the basis of a first polynomial for a first extension from a first finite field to a second finite field; a second step of obtaining a second primitive root α₂ on the basis of a second polynomial for a second extension from the second finite field to a third finite field, in which a coefficient of a 0-th term is defined using the first primitive root α₁ obtained in the first step and the coefficient of the 0-th term of the first polynomial; a third step of defining the processing on the third finite field using a base expressed using the second primitive root α₂ obtained in the second step; and a fourth step of designing a processing circuit for the related processing on the basis of the processing defined in the third step.

[0012] The mode of operation of the circuit design method of the first aspect of the invention therefore becomes as follows.

[0013] First, in the first step, a first primitive root a is obtained on the basis of a first polynomial for a first extension from a first finite field to a second finite field.

[0014] Next, in the second step, a second primitive root α₂ is obtained on the basis of a second polynomial for a second extension from the second finite field to a third finite field, in which the coefficient of the 0-th term is defined using the first primitive root α₁ obtained in the first step and the coefficient of the 0-th term of the first polynomial.

[0015] Next, in the third step, processing on the third finite field is defined using a base expressed by using the second primitive root α₂ obtained in the second step.

[0016] Next, in the fourth step, on the basis of the processing defined in the third step, a processing circuit for the related processing is designed.

[0017] According to a second aspect of the present invention, there is provided a circuit design apparatus for designing a processing circuit for processing on a finite field comprising: a first means for obtaining a first primitive root α₁ on the basis of a first polynomial for a first extension from a first finite field to a second finite field; a second means for obtaining a second primitive root α₂ on the basis of a second polynomial for a second extension from the second finite field to a third finite field, in which a coefficient of a 0-th term is defined using the first primitive root α₁ obtained by the first means and the coefficient of the 0-th term of the first polynomial; a third means for defining processing on the third finite field using a base expressed using the second primitive root α₂ obtained by the second means; and a fourth means for designing a processing circuit for the related processing on the basis of the processing defined by the third means.

[0018] The mode of operation of the circuit design apparatus of the second aspect of the invention becomes as follows.

[0019] First, in the first means, a first primitive root α₁ is obtained on the basis of a first polynomial for a first extension from a first finite field to a second finite field.

[0020] Next, in the second means, a second primitive root α₂ is obtained on the basis of a second polynomial for a second extension from the second finite field to a third finite field, in which the coefficient of a 0-th term is defined using the first primitive root α₁ obtained by the first means and the coefficient of the 0-th term of the first polynomial.

[0021] Next, in the third means, processing on the third finite field is defined using a base expressed by using the second primitive root α₂ obtained by the second means.

[0022] Next, in the fourth means, on the basis of the processing defined in the third means, a processing circuit for the related processing is designed.

[0023] According to a third aspect of the present invention, there is provided a program executed by the circuit design apparatus for designing a processing circuit for processing on a finite field comprising a first routine of obtaining a first primitive root α₁ on the basis of a first polynomial for a first extension from a first finite field to a second finite field; a second routine of obtaining a second primitive root α₂ on the basis of a second polynomial for a second extension from the second finite field to a third finite field, in which a coefficient of a 0-th term is defined using the first primitive root α₁ obtained in the first routine and the coefficient of the 0-th term of the first polynomial; a third routine of defining processing on the third finite field using a base expressed using the second primitive root α₂ obtained in the second routine; and a fourth routine of designing a processing circuit for the related processing on the basis of the processing defined in the third routine.

BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The above object and features of the present invention will be more apparent from the following description of the preferred embodiments given with reference to the accompanying drawings, wherein:

[0025]FIG. 1 is a view for explaining a processing circuit for processing on a finite field L designed by a circuit design method of the related art of the present invention;

[0026]FIG. 2 is a view of the configuration of an a-times multiprocessing circuit on a finite field K shown in FIG. 1;

[0027]FIG. 3 is a view for explaining a processing circuit for processing on a finite field L designed by a circuit design method of an embodiment of the present invention;

[0028]FIG. 4 is a view for explaining a computer for executing the circuit design method of the embodiment of the present invention;

[0029]FIG. 5 is a view for explaining processing of the computer shown in FIG. 4; and

[0030]FIG. 6 is a view of the configuration of the a-times multiprocessing circuit on the finite field K shown in FIG. 3.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0031] [Related Art of Invention]

[0032] As a related art, for reference, an explanation will be given of a circuit design method for designing a processing circuit for processing on a finite field L including a-times multiprocessing on a finite field K in a case where a finite field F is an n-th extension of a finite field F_(q), a finite field K is an extension of the extension order q from the finite field F, and a finite field L is an extension of the extension order q from the finite field K.

[0033] Here, the order is indicated by the following (1-1), and the finite field L is expressed as in the following (1-2). In the present embodiment, in the following (1-1) and (1-2), a case where l₁=l₂=q is exemplified.

q ^(n·l) ^(₁) ^(·l) ^(₂) (q=p ^(m) , p: prime number, n, l ₁ , l ₂ , m: natural numbers)  (1-1)

L:=F _(q) _(^(n·l)) ₁ _(^(·l)) ₂  (1-2)

[0034] In this case, the relationships of the above extensions are indicated by the following (1-3): $\begin{matrix} {\left( {F_{q}\quad \begin{matrix} \begin{matrix} {n\text{-}{th}} \\ {dimensional} \end{matrix} \\  \Subset  \end{matrix}} \right)\quad F\quad \begin{matrix} \begin{matrix} \begin{matrix} \begin{matrix} (1) \\ {q\text{-}{th}} \end{matrix} \\ {dimensional} \end{matrix} \\ {extension} \end{matrix} \\ {\Subset \begin{matrix} \quad \\ \quad \end{matrix}} \end{matrix}\quad K\quad \begin{matrix} \begin{matrix} \begin{matrix} \begin{matrix} (2) \\ {q\text{-}{th}} \end{matrix} \\ {dimensional} \end{matrix} \\ {extension} \end{matrix} \\ {\Subset \begin{matrix} \quad \\ \quad \end{matrix}} \end{matrix}\quad L} & \left( {1\text{-}3} \right) \end{matrix}$

[0035] In the related circuit design method, as shown in FIG. 1, a processing circuit 300 receiving as input an l₂-th dimensional vector D_IN on the finite field K, outputting an l₂-th dimensional vector D_OUT on the finite field K, having an a-times multiprocessing circuit 301 on the finite field K, and processing on the finite field L is designed.

[0036] The a-times multiprocessing circuit 301 on the finite field K receives as input an l₁-th dimensional vector VA on the finite field F and outputs an l₁-th dimensional vector VD on the finite field F.

[0037] A primitive root α₁ of the first extension K/F from the finite field F to the finite field K is obtained on the basis of a first polynomial shown in the following (1-4):

α₁:α₁ ^(q)−α₁ +c=0, ∃c∈Fs.t.Tr _(F) _(q) ^(F)(c)≠0,  (1-4)

[0038] Then, the base of the processing on the finite field K is selected on the basis of the primitive root α₁,.

[0039] Further, a primitive root α₂ of the second extension L/K from the finite field K to the finite field L is obtained on the basis of a second polynomial shown in the following (1-5).

α₂:α₂ ^(q)−α₂ +a=0, ∃a=d·α ₁ ^(i) ∈K, i∈Zs.t.Tr _(F) _(q) ^(K)(α₁ ^(i))≠0,  (1-5)

[0040] Then, the base of the processing on the finite field L is selected on the basis of the primitive root α₂.

[0041] Here, the “a” of the a-times multiprocessing circuit 301 is the coefficient “a” of the 0-th term in (1-5).

[0042] Then, any dimension A on the finite field K shown in the following (1-6) using the base determined on the basis of the above primitive root α₁ is shown by the l₁(=q)-th dimensional vector VA on the finite field F as in the following (1-7):

A: A ₀ +A ₁ α ₁ +A ₂α₁ ² + . . . +A _(q−1)α₁ ^(q−1)  (1-6)

VA:=(A ₀ , A ₁ , A ₂ , . . . , A _(q−1))  (1-7)

[0043] Further, D shown by the following (1-8) using the base determined on the basis of the above primitive root α₁ is shown by the l₁(=q)-th dimensional vector VD on the finite field F as in the following (1-9):

D:=a·A=D ₀ +D ₁α₁ ² + . . . , +D _(q−1)α₁ ^(q−1)  (1-8)

VD:=(D ₀ , D ₁ , D ₂ , . . . , D _(q−1))  (1-9)

[0044] In this case, D:=a·A becomes as shown in the following (1-10) and the vector VD becomes as shown in the following (1-11) when using “a” defined by the above (1-5) and A defined by the above (1-6). Here, the “q” power of μ₁ of the left side of the following (1-12) is expressed replaced by the value (α₁−1) of the right side. $\begin{matrix} \begin{matrix} {{{- c}\quad {d \cdot A_{q - i} \cdot \alpha_{1}^{0}}} + {\sum\limits_{k = 1}^{i - 1}\quad \left\{ {\left( {{d \cdot A_{k + q - i - 1}} - {c\quad {d \cdot A_{k + {q\quad \ldots \quad i}}}}} \right) \cdot \alpha_{1}^{k}} \right\}} +} \\ {{{d\left( {A_{0} + A_{q - 1}} \right)} \cdot \alpha_{1}^{i}} + {d{\sum\limits_{k = {i + 1}}^{q - 1}\quad \left\{ {A_{k - i} \cdot \alpha_{1}^{k}} \right\}}}} \end{matrix} & \left( {1\text{-}10} \right) \\ \begin{matrix} \begin{matrix} \left\{ {{{- c}\quad d\quad A_{q - i}},{{d\quad A_{1 + q - i - 1}} - {c\quad d\quad A_{{1 + q - i},}\quad d\quad A_{2 + q - i - 1}}\quad -}} \right. \\ {{c\quad d\quad A_{2 + q - i}},\ldots \quad,{{d\quad A_{i - 1 + q - i - 1}} - {c\quad d\quad A_{{i - 1 + q - i},}\quad {d\left( {A_{0} + A_{q - 1}} \right)}}},} \end{matrix} \\ \left. {{d\quad A_{i + 1 - i}},\quad {d\quad A_{i + 2 - i}},{\ldots \quad d\quad A_{q - 1 - i}}} \right\} \end{matrix} & \left( {1\text{-}11} \right) \\ {\alpha_{1}^{q} = {\alpha_{1} - c}} & \left( {1\text{-}12} \right) \end{matrix}$

[0045] In the above circuit design method, as shown in FIG. 2, the a-times multiprocessing circuit 301 on the finite field K shown in FIG. 1 is designed on the basis of above (1-10) and (1-11).

[0046] The a-times multiprocessing circuit 301 shown in FIG. 2 has input to it the q-th dimensional vector VA shown in the above (1-7).

[0047] A[0] to A[q−1] shown in FIG. 2 correspond to A₀ to A_(q−1) shown in the above (1-7).

[0048] The a-times multiprocessing circuit 301 is designed so as to perform the processing shown in the above (1-10) by replacing the q-th term of α₁ by the first and the 0-th terms on the basis of (1-12) obtained from (1-4).

[0049] Due to this, the a-times multiprocessing circuit 301 is designed so as to perform processing for the coefficient of less than the q-th term of α₁.

[0050] As shown in FIG. 2, the above circuit design method designs the a-times multiprocessing circuit 301 so that data A[0] to A[q−1] are input to the corresponding circuits among the q−1 number of multiplier circuits 31_1 to 31 _(—) q−1 for multiplying with the coefficient “d”, the i−1 number of multiplier circuits 32_1 to 32 _(—) i−1 for multiplying with the coefficient cd, and an adder circuit 33.

[0051] Further, the above circuit design method designs the a-times multiprocessing circuit 301 so that the outputs of the multiplier circuits 32_0 to 32 _(—) i−1 are input to inverters 35_0 to 35 _(—) i−1.

[0052] Further, the above circuit design method designs the a-times multiprocessing circuit 301 so that the outputs of the multiplier circuits 31_1 to 31 _(—) i−1 are input to adder circuits 34_1 to 34 _(—) i−1.

[0053] Further, the above circuit design method designs the a-times multiprocessing circuit 301 so that the outputs of the inverters 35_1 to 35 _(—) i−1 are input to the adder circuits 34_1 to 34 _(—) i−1.

[0054] Further, the above circuit design method designs the a-times multiprocessing circuit 301 so that the output of the multiplier circuit 33 is input to the multiplier circuit 32 for multiplying with the coefficient “d”.

[0055] Then, the outputs of the inverter 35_0, the adder circuits 34_1 to 34 _(—) i−1, the multiplier circuit 32, and the multiplier circuits 31 _(—) i to 31 _(—) q−1 become the data D[0] to D[q−1].

[0056] D[0] to D[q−1] shown in FIG. 2 correspond to D₀ to D_(q−1) shown in the above (1-9) and (1-11).

[0057] [Embodiments of the Invention]

[0058] In the present embodiment, in the same way as the related art, an explanation will be given of a circuit design method for designing a processing circuit for processing a finite field L including a-times multiprocessing on a finite field K in the case where a finite field F (first finite field of the present invention) is an n-th extension of the finite field F_(q), the finite field K (second finite field of the present invention) is an extension of an extension order “q” from the finite field F, and the finite field L (third finite field of the present invention) is an extension of the extension order “q” from the finite field K.

[0059] Here, the order is indicated by (2-1), and the finite field L is expressed as in the following (2-2). In the present embodiment, in the following (2-1) and (2-2), the case where l₁=l₂=q will be exemplified. For example, “q” is 2, and “n” is 4.

q ^(n·l) ^(₁) ^(·l) ^(₂) (q=p ^(m), p: prime number, n, l₁ , l ₂ , m: natural numbers)  (2-1)

L:=F _(q) _(^(n·l)) ₁ _(^(·l)) ₂  (2-2)

[0060] In this case, the relationships of the above extensions are indicated by the following (2-3): $\begin{matrix} {\left( {F_{q}\quad \begin{matrix} \begin{matrix} {n\text{-}{th}} \\ {dimensional} \end{matrix} \\  \Subset  \end{matrix}} \right)\quad F\quad \begin{matrix} \begin{matrix} \begin{matrix} \begin{matrix} (1) \\ {q\text{-}{th}} \end{matrix} \\ {dimensional} \end{matrix} \\ {extension} \end{matrix} \\ {\Subset \begin{matrix} \quad \\ \quad \end{matrix}} \end{matrix}\quad K\quad \begin{matrix} \begin{matrix} \begin{matrix} \begin{matrix} (2) \\ {q\text{-}{th}} \end{matrix} \\ {dimensional} \end{matrix} \\ {extension} \end{matrix} \\ {\Subset \begin{matrix} \quad \\ \quad \end{matrix}} \end{matrix}\quad L} & \left( {2\text{-}3} \right) \end{matrix}$

[0061] In the circuit design method of the present embodiment, as shown in FIG. 3, a processing circuit 100 receiving as input the l₂(=q)-th dimensional vector D_IN on the finite field K, outputting the l₂-th dimensional vector D_OUT on the finite field K, having the a-times multiprocessing circuit 101 on the finite field K, and performing processing on the finite field L is designed.

[0062] The a-times multiprocessing circuit 101 on the finite field K receives as input the l₁(=q)-th dimensional vector VA on the finite field F and outputs the l₁-th dimensional vector VD on the finite field F.

[0063] The first primitive root α₁ (first primitive root of the present invention) of the first extension K/F (first extension of the present invention) from the finite field F to the finite field K is obtained on the basis of the first polynomial shown in the following (2-4):

α ₁:α₁ ^(q)−α₁ +c=0, ∃c∈Fs.t.Tr _(F) _(q) ^(F)(c)≠0,  (2-4)

[0064] Then, the base of the processing on the finite field K is selected on the basis of the primitive root α₁.

[0065] In the above (2-4), a trace Tr is defined as in the following (2-4a).

Tr _(F) _(q) ^(F)(c):=c+c ^(q) +c ^(q) ² c ^(q) ³ + . . . +c ^(q) ^(n1)   (2-4a)

[0066] Further, the second primitive root α₂ (second primitive root of the present invention) of the second extension L/K (second extension of the present invention) from the finite field K to the finite field L is obtained on the basis of the second polynomial (second polynomial of the present invention) shown in the following (2-5).

α₂:α₂ ^(q)−α₂ +a=0, ∃a=c ⁻¹·α₁ ^(i) ∈K, i∈Zs.t.Tr _(F) _(q) ^(K)(α₁ ^(i))≠0,  (2-5)

[0067] Here, in the second polynomial shown in (2-5), the coefficient “a” of the 0-th term is defined by using the first primitive root α₁ of the first polynomial shown in the above (2-4) and the coefficient “c” of the 0-th term of the first polynomial.

[0068] Then, the dimension A on the finite field K shown in the following (2-6) using the base determined on the basis of the first primitive root α₁ is shown by the l₁-th dimensional vector VA on the finite field F as in the following (2-7).

A:A ₀ A ₁α₁ +A ₂α₁ ² + . . . +A _(q−1)α₁ ^(q−1)  (2-6)

VA:=(A ₀, A₁, A₂, . . . , A_(q−1))  (2-7)

[0069] Further, D shown in the following (2-8) using the base determined on the basis of the above first primitive root α₁ is indicated by the l₁-th dimensional vector VD on the finite field F as in the following (2-9):

D:=a·A=D ₀ +D ₁α₁ +D ₂α₁ ² + . . . +D _(q−1)α₁ ^(q−1)  (2-8)

VD:=(D ₀ , D ₁ , D ₂ , . . . D _(q−1))  (2-9)

[0070] In this case, when using “a” defined by the above (2-5) and A defined by the above (2-6), D:=a·A becomes as shown in the following (2-10), and the vector V_D becomes as shown by the following (2-11). Here, the “q” power of α₁ of the left side of the following (2-12) obtained from the above (2-4) is expressed replaced by the value (α₁−1) of the right side. $\begin{matrix} \begin{matrix} {{D\text{:}} = {a \cdot A}} \\ {= {{{- A_{l_{1\quad i}}} \cdot \alpha_{1}^{0}} + {\sum\limits_{k = 1}^{i - 1}\quad \left\{ {\left( {{c^{- 1} \cdot A_{k + l_{1} - i - 1}} - A_{k + l_{1} - i}} \right) \cdot \alpha_{1}^{k}} \right\}} +}} \\ {{{{c^{- 1}\left( {A_{0} + A_{l_{1} - 1}} \right)} \cdot \alpha_{1}^{i}} + {c^{- 1}{\sum\limits_{k = {i + 1}}^{l_{1} - 1}\quad {\left\{ {A_{k - i} \cdot \alpha_{1}^{k}} \right\}.}}}}} \end{matrix} & \left( {2\text{-}10} \right) \\ \begin{matrix} \begin{matrix} \left( {{{{- A_{l_{1\quad \ldots \quad i},}}c^{- 1}A_{1 + l_{1} - i - 1}} - A_{1 + l_{1} - i}},{{c^{- 1}A_{2 + l_{1} - i - 1}} -}} \right. \\ {A_{2 + l_{1} - i},\ldots \quad,{{c^{- 1}A_{i - 1 + l_{1} - i - 1}} - A_{i - 1 + l_{1} - i}},{c^{- 1}\left( {A_{0} + A_{l_{1} - 1}} \right)},} \end{matrix} \\ \left. {{c^{- 1}A_{i + 1 - i}},{c^{- 1}A_{i + 2 - i}},\ldots \quad,{c^{- 1}A_{l_{1} - 1 - i}}} \right) \end{matrix} & \left( {2\text{-}11} \right) \\ {\alpha_{1}^{q} = {\alpha_{1} - c}} & \left( {2\text{-}12} \right) \end{matrix}$

[0071] In the above circuit design method, as shown in FIG. 1, the a-times multiprocessing circuit 101 on the finite field K is designed on the basis of above (2-10) and (2-11).

[0072] Here, “a” of the a-times multiprocessing circuit 101 is the “a” in the above (2-5).

[0073]FIG. 4 is a view of the configuration of a computer 29 (circuit design apparatus of the present invention) for executing the circuit design method of the present embodiment.

[0074] As shown in FIG. 4, the computer 29 has for example an operating unit 31, a display 32, a memory 33, and a CPU 34 all connected via a bus 30.

[0075] The operating unit 31 is an operating means such as a keyboard or a mouse and outputs an operating signal in accordance with operations by the user to the CPU 34. The display 32 displays a screen corresponding to the processing of the circuit design by the CPU 34.

[0076] The memory 33 stores a program 41 (program of the present invention) and data 42 used for the processing of the CPU 34.

[0077] The CPU 34 executes the program 41 and designs the a-times multiprocessing circuit on the finite field K in the processing circuit on the finite field L as shown below by using the data 42.

[0078] The CPU 34 corresponds to the first to fourth means of the circuit design apparatus of the present invention.

[0079]FIG. 5 is a flow chart for explaining an example of the operation in the case where the CPU 34 designs the multiplier circuits in the processing circuit 2.

[0080] Step ST1

[0081] The CPU 34 obtains the first primitive root α₁ on the basis of the first polynomial shown in the above (2-4) for the first extension from the finite field F to the finite field K.

[0082] Step ST2

[0083] The CPU 34 obtains above second primitive root α₂ on the basis of the second polynomial shown in the above (2-5) in which the coefficient “a” of the 0-th term is defined by using the first primitive root α₁ obtained at step ST1 and the coefficient of the 0-th term of the first polynomial.

[0084] Step ST3

[0085] The CPU 34 defines the processing on the finite field L by using the base expressed by using the above primitive root α₂ obtained at step ST2.

[0086] Then, when there is a-times multiprocessing on the finite field K in the processing on the finite field L, the a-times multiprocessing is defined on the basis of the above (2-10) and (2-11). At this time, on the basis of above (3-12), the q-th term of α₁ in the above (2-10) is replaced by the coefficients “c” of the first and 0-th terms to define the related a-times multiprocessing. By this, the above a-times multiprocessing is defined by processing for the coefficients of the less than q-th terms of α₁.

[0087] Step ST4

[0088] The CPU 34 designs the processing circuit for the above processing on the finite field L including the a-times multiprocessing circuit on the above finite field K on the basis of the processing defined at step ST3.

[0089] In the present embodiment, for example, the a-times multiprocessing circuit 101 on the finite field K shown in FIG. 3 is designed as shown in FIG. 6.

[0090] Namely, the a-times multiprocessing circuit 101 is designed so that the CPU 34 receives as input the q-th dimensional vector VA shown in the above (2-7).

[0091] A[0] to A[q−1] shown in FIG. 6 correspond to A₀ to A_(q−1) shown in the above (2-7).

[0092] Further, as shown in FIG. 6, the CPU 34 designs the a-times multiprocessing circuit 101 so that the data A[0] to A[q−1] are input to the corresponding circuits among the inverters 13_0 to 13_(—) i−1, c-⁻¹-multiprocessing circuits 11_1 to 11_(—) i−1, and c-⁻¹-multiprocessing circuits 11 _(—) i+1 to 11_(—) q−1 for the c-⁻¹-multiprocessing, and the adder circuit 12.

[0093] Further, the CPU 34 designs the a-times multiprocessing circuit 101 so that the outputs of the c⁻¹-multiprocessing circuits 11_1 to 11 _(—) i−1 are input to the adder circuits 14_1 to 14 _(—) i−1.

[0094] Further, the CPU 34 designs the a-times multiprocessing circuit 101 so that the outputs of the inverters 13_1 to 13 _(—) i−1 are input to the adder circuits 14_1 to 14 _(—) i−1.

[0095] Further, the CPU 34 designs the a-times multiprocessing circuit 101 so that the output of the adder circuit 12 is input to the c⁻¹-multiprocessing circuit 11 ⁻ i.

[0096] Then, the CPU 34 designs the a-times multiprocessing circuit 101 so that the outputs of the inverter 13_0, adder circuits 14_1 to 14 _(—) i−1, and c⁻¹-multiprocessing circuits 11 _(—) i to 11 _(—) q−1 become the data D[0] to D[q−1].

[0097] D[0] to D[q−1] shown in FIG. 6 correspond to D₀ to D_(q−1) shown in the above (2-9) and (2-11).

[0098] As explained above, according to the circuit design method of the present embodiment, as shown in the above (2-5), by defining the coefficient “a” of the 0-th term of the second polynomial by using the first primitive root α₁ of the first polynomial shown in the above (2-4) and the coefficient c of the 0-th term of the related first polynomial, the a-times multiprocessing circuit 101 shown in FIG. 6 having a decreased number of circuit elements and reduced size in comparison with the a-times multiprocessing circuit 301 shown in FIG. 2 can be designed. In the conventional a-times multiprocessing circuit 301 shown in FIG. 2, the circuit for performing the multiplication concerned with the coefficient “c”, shown in the above (1-4) and the coefficient “d” shown in the above (1-5) was needed as the X-multiprocessing circuit, but in the a-times multiprocessing circuit 101, the X-multiprocessing circuit becomes only the circuit concerned with the coefficient “c”.

[0099] The present invention is not limited to the above embodiment.

[0100] For example, in the above (2-4) and (2-5), when q=2 and n=4, the first finite field F is shown by the following (3-1), and the above (2-4) and (2-5) are shown by the following (3-2) and (3-3):

F=F ₂(γ),γ⁴+γ+1=0  (3-1)

α₁:α₁ ²+α₁ +c=0, c=γ ³  (3-2)

α₂:α₂ ²+α₂ +a=0, a=γ ^(−3.)α₁  (3-3)

[0101] Further, in the above embodiment, the case of designing a processing circuit on the finite field L including the a-times multiprocessing circuit on the finite field K was illustrated, but the present invention can also design a processing circuit on the finite field L including a multiplier circuit on the finite field K and an inverse element generation circuit.

[0102] Summarizing the effects of the invention, according to the present invention, it is possible to provide a circuit design method, apparatus, and program able to design a processing circuit for processing on a finite field with fewer circuit design elements and in a smaller size than the past and such a processing circuit.

[0103] While the invention has been described with reference to specific embodiments chosen for purpose of illustration, it should be apparent that numerous modifications could be made thereto by those skilled in the art without departing from the basic concept and scope of the invention. 

1. A circuit design method executed by a computer for designing a processing circuit for processing on a finite field comprising: a first step of obtaining a first primitive root α₁ on the basis of a first polynomial for a first extension from a first finite field to a second finite field; a second step of obtaining a second primitive root α₂ on the basis of a second polynomial for a second extension from said second finite field to a third finite field, in which a coefficient of a 0-th term is defined using said first primitive root α₁ obtained in said first step and the coefficient of the 0-th term of said first polynomial; a third step of defining the processing on said third finite field using a base expressed using said second primitive root α₂ obtained in said second step; and a fourth step of designing a processing circuit for the related processing on the basis of the processing defined in said third step.
 2. A circuit design method as set forth in claim 1, wherein when: said first finite field is an extension of an extension order n from a finite set F_(q), said second finite field is a first extension of an extension order l₁ from said first finite field, said third finite field is a second extension of an extension order l₂ from said second finite field, and defining the processing on said third finite field shown by the following (1-2) of the order shown by the following (1-1) in the third step, the method obtains said first primitive root α₁ on the basis of the following (1-3) in the first step and obtains said second primitive root α₂ on the basis of the following (1-4) in the second step: q ^(n·l) ^(₁) ^(l) ^(₂) (q=p ^(m) , p: prime number, n, l ₁ , l ₂ , m: natural numbers)  (1-1) L:=F _(q) _(^(n·l)) ₁ _(^(·l)) ₂  (1-2) α ₁:α₁ ^(l) ^(₁) −α₁ +c=0, X ^(l) ^(₁) −X+c∈F[X], Irreducible  (1-3) α₂:α₂ ¹ ^(₂) −α₂ +a=0, a=c ⁻¹·α₁ ^(i) ·∃i∈Z,s.t.X ¹ ^(₂) −X+a∈K[X], Irreducible  (1-4)
 3. A circuit design method as set forth in claim 2, wherein, when said extension orders 1 ₁ and l₂ are both q, the method obtains said first primitive root α₁ on the basis of the following (1-5),. (1-5a) in the first step and obtains said second primitive root α₂ on the basis of the following (1-6) in the second step: α₁:α₁ ^(q)−α₁ +c=0, ∃c∈Fs.t.Tr _(F) _(q) ^(F)(c)≠0  (1-5) Tr _(F) _(q) ^(F)(c):=c+c ^(q) +c ^(q) ² c ^(q) ³ + . . . +c ^(q) ^(n·1)   (1-5a) α₂:α₂ ^(q)−α₂ +a=0, ∃a=c ⁻¹·α₁ ^(i) ∈K, i∈Zs.t.Tr _(F) _(q) ^(K)(α₁ ^(i))≠0,  (1-6)
 4. A circuit design method as set forth in claim 1, further comprising: defining processing on said third finite field using processing on said second finite field in said third step and designing a first processing circuit for processing on said second finite field used in said third step and designing a second processing circuit for processing on said third finite field using said first processing circuit.
 5. A circuit design method as set forth in claim 4, further comprising defining processing on said third finite field using processing on said second finite field multiplying a coefficient of the 0-th term of said second polynomial in said third step.
 6. A circuit design apparatus for designing a processing circuit for processing on a finite field comprising: a first means for obtaining a first primitive root α₁ on the basis of a first polynomial for a first extension from a first finite field to a second finite field; a second means for obtaining a second primitive root α₂ on the basis of a second polynomial for a second extension from said second finite field to a third finite field, in which a coefficient of a 0-th term is defined using said first primitive root α₁ obtained by said first means and the coefficient of the 0-th term of said first polynomial; a third means for defining processing on said third finite field using a base expressed using said second primitive root α₂ obtained by said second means; and a fourth means for designing a processing circuit for the related processing on the basis of the processing defined by said third means.
 7. A program executed by the circuit design apparatus for designing a processing circuit for processing on a finite field comprising: a first routine of obtaining a first primitive root α₁ on the basis of a first polynomial for a first extension from a first finite field to a second finite field; a second routine of obtaining a second primitive root α₂ on the basis of a second polynomial for a second extension from said second finite field to a third finite field, in which a coefficient of a 0-th term is defined using said first primitive root α₁ obtained in said first routine and the coefficient of the 0-th term of said first polynomial; a third routine of defining processing on said third finite field using a base expressed using said second primitive root α₂ obtained in said second routine; and a fourth routine of designing a processing circuit for the related processing on the basis of the processing defined in said third routine. 